The present invention relates generally to computer systems, and more specifically, to built-in testing of an unused element on a chip in a computer system.
An additional amount of margin may be added to the performance criteria of a semiconductor chip during testing at the end of the manufacturing process, as the chip may be negatively influenced by degradation of performance. However, the chip will only need the added margin if critical path(s) are negatively affected, which does not always occur. Therefore, in the absence of degradation in the semiconductor chip, the added margin may comprise one or more unused elements on the chip.
Solid state memory arrays are frequently used in computers and other electronic devices where fast access times are desired. For example, solid state memory arrays are often used as the main working storage repository for a computer, as well as in higher speed cache memories, implemented either separate from or in the same integrated circuit device as the principal processing circuitry for the computer.
Solid state memory arrays are typically implemented on a semiconductor integrated circuit device using multiple memory cells assigned to different memory addresses and arranged together with support circuitry suitable for accessing specific memory cells in the array. Due to processing variations that are inherent in all semiconductor manufacturing processes, it is not uncommon for one or more memory cells in a manufactured memory array to be faulty, and thus be incapable of reliably storing information. While a memory array may contain thousands or millions of memory cells, if even one memory cell in the memory array is faulty, the entire memory array is essentially unusable.
To address this concern, a portion of the memory cells in many memory array designs are designated as “redundant” memory cells that are selectively used to repair the memory arrays whenever primary memory cells are found to be faulty. Typically, such repairs are made by selectively activating fuses disposed on the same integrated circuit device as a memory array. Often, a fuse is implemented as a conductive interconnect that is selectively (and permanently) broken using a laser or an excessive electrical current. The fuse is coupled to routing logic for the memory array, such that, when the fuse conducts, a primary memory cell, or bank of primary memory cells, are accessed whenever a specific memory address associated with such a cell is requested. However, whenever the fuse is broken, the routing logic will instead access a redundant memory cell, or bank of redundant memory cells, in place of the primary memory cell(s) associated with that memory address.
Through the use of redundant memory cells, the manufacturing yield of semiconductor devices incorporating memory arrays can be significantly improved, since memory arrays containing relatively minor faults can be repaired, rather than having to be completely scrapped. Particularly when a memory array is integrated onto the same integrated circuit device as a complex and expensive logic circuit (e.g., as a level one cache for use with a microprocessor core), the cost savings associated with fuse-based repairs can be substantial. If such a repair is carried out after the semiconductor device is delivered to the field, the longevity of the semiconductor devices may be enhanced. This redundancy is not limited to just memory cells. There may be redundant processor units, redundant memory arrays, entire redundant processor cores, or other redundant elements on a chip. A primary, now defective element may be deactivated through a logical masking process and become a masked element.